1. Field of the Invention
This invention relates generally to fabrication of barium strontium titanate (BST) thin film devices, and more particularly, to passivation of BST thin film capacitors and fabrication of BST thin film resistors.
2. Description of the Related Art
Fabrication processes for semiconductor devices usually include one or more passivation layers. Passivation layers may be used, for example, to separate active components or active layers, such as metal lines. They can also be used as the dielectric for MIM or inter-digital capacitors. Additionally, passivation layers may be used to prevent contamination of, and enhance the reliability of, the final fabricated device.
The materials used for the passivation layers are usually chosen based on process availability, compatibility with previous processing, and desired characteristics. In particular, materials that can be utilized in other parts of the design are preferable to reduce design complexity and to minimize manufacturing costs. Typical examples of passivation layer materials include silicon nitride (Si3N4), silicon dioxide (SiO2), and aluminum oxide (Al2O3). Si3N4 is desirable for its ability to define small critical dimensions, but its thickness may be limited due to stress effects. In contrast, SiO2 may be used for thicker layers with fewer stress effects.
The passivation layers used in fabrication processes are intended to have little or no effect on the behavior and characteristics of underlying devices. In practice, however, the interface between the passivation layer and other active layers may produce paths for leakage currents to flow. These paths, also called “leakage paths,” are undesirable for power efficiency and reliability.
FIG. 1 is a cross-sectional view of an integrated circuit 100 fabricated using semiconductor process technology including a conventional passivation scheme. Integrated circuit 100 includes a tunable BST capacitor 105 and a fixed capacitor 110. Capacitors, which are a basic building block for electronic circuits, may be fabricated in various configurations. One design for capacitors is the parallel-plate configuration, in which a dielectric is sandwiched between two electrodes, as shown for capacitors 105, 110 in FIG. 1. The use of semiconductor process technology allows the fabrication of many capacitors on a single wafer and also permits the integration of capacitors with other circuitry.
In FIG. 1, the tunable BST capacitor 105 includes a bottom electrode 115, which may be a conducting layer such as a metal, formed on a substrate 120. A ferroelectric BST thin film dielectric layer 125 is sandwiched between the bottom electrode 115 and a top electrode 130, which may be another metal layer. An additional conductive layer 135 may be provided to form a low resistance contact to the top electrode 130. A first passivation layer 140 protects the bottom electrode 115, the dielectric layer 125, and the top electrode 130. Because of the high dielectric constant of BST, the top electrode 130 is sometimes small in physical dimension, requiring the first passivation layer 140 to have excellent step coverage and to be capable of patterning small critical dimensions. For semiconductor processes, Si3N4 is often used, although SiO2 and Al2O3 may also be used. A second passivation layer 145 protects the entire structure, and includes openings 150 to allow electrical contact to the BST capacitor 105.
The fixed capacitor 110 includes a bottom electrode 155, which may be formed using the same conducting layer as the bottom electrode 115 of the BST capacitor 105. The passivation layer 140 serves as the dielectric layer for the fixed capacitor 110, while the conductive layer 135 serves as the top electrode for the fixed capacitor 110.
A major drawback to conventional passivation of the BST capacitor 105, however, is the formation of a leakage path 160 along the interface of the dielectric layer 125 and the first passivation layer 140, as shown in FIG. 1. This leakage path 160 between the top electrode 130 and the bottom electrode 115 can be undesirable for power efficiency and reliability, particularly if it is uncontrolled.
Thus, there is a need to reduce and/or control the leakage path formed along the interface of the ferroelectric dielectric layer between the electrodes of ferroelectric thin film devices.